FPGA

The FPGA node abstracts programmable Field-programmable gate array.

Attributes

They have the following attributes.

Scheduling

Let us assume that n tasks have been mapped to a FPGA.

If the Scheduling attribute is left empty, the system assumes that all tasks mapped to the FPGA can be executed at the same time, in parallel. Said differently, the designer thinks that all tasks can fit at the same time in the FPGA.

IF all tasks cannot fit at the same time in the FPGA matrix, then the design can give a static schedule that represents in which sequence tasks are executed.

A scheduling is described by sets of tasks executed together, separated by “;”.

For instance: T1 T2 ; T3 ; T4 T5

A “;” means that the FPGA performs a dynamic reconfiguration before switching to the next set of tasks. The FPGA switches to the next set of tasks only once the tasks of the previous set have all terminated their execution.